Xilinx Zynq 7020 FPGA
- Three Phase Full-Wave Controller Bridge Rectifier
- Creating a Custom AXI4 IP Block in Vivado
- Zedboard GPIOs Control via AXI4 Peripheral
- AXI4 IP Peripheral for Controlling SCRs Delay Angle
- Zedboard AXI GPIO IP Peripheral
- 16×16 Bits 4-Stage Pipelined Multiplier
Lattice MachXO2 FPGA
- Writing My Own Slave SPI Interface in VHDL
- SPI Slave Peripheral Using Lattice Embedded Function Block
- Driving Eight Addressable RGB LEDs in VHDL
Kintex-7/Spartan-7/Zynq UltraScale Projects
- Frequency Sweep from 1–500 KHz with DDS IP Core
- Infinite Impulse Response Filter Design on FPGA
- Sixth Order IIR Filter Design with Three Cascaded Biquads in VHDL
- High Speed IIR Filter Design With DSP Slices
- FIR Filter Design in Vivado, Tested With DDS Sweep
- FM Modulation with DDS in Xilinix Vivado
- FM Demodulation of a 10.7MHz IF Frequency
- AM Modulation with DDS in Xilinix Vivado
- AM DeModulation with DDS in Xilinix Vivado
- How Xilinx DDS Works on an FPGA: Math Derivation
- Cross Clock Domain Violation In FPGA, Part 1
- Cross Clock Domain Violation In FPGA, Part 2
- Bandpass Sampling: How to Digitise a 10.7 MHz IF FM Radio Signal With a 10 MHz ADC Sampling Frequency
- FPGA Based Upconversion From Digital IF to RF
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