AM Demodulation with DDS in Vivado

Project Overview

In this project, I will demonstrate how to implement Amplitude Modulation (AM)
demodulation using a Direct Digital Synthesizer (DDS) in Xilinx Vivado.
The design focuses on digital signal processing techniques implemented
on FPGA hardware.

Objectives

• Understand the principles of AM modulation and demodulation.
• Generate a carrier signal using DDS.
• Demodulate an AM signal using digital techniques.
• Implement and simulate the design in Xilinx Vivado.

Tools and Technologies

• Xilinx Vivado Design Suite
• FPGA (Xilinx-based)
• Verilog or VHDL for hardware description
• DDS IP Core

Digital AM Demodulation

In digital AM demodulation, the incoming AM signal is sampled and represented as digital values. The FPGA multiplies the digitized signal with a DDS-generated carrier and applies a digital low-pass filter to recover the message signal.

• Sampling: Convert the AM signal into discrete-time digital values using an ADC.
• Carrier Generation: Generate a reference carrier using DDS.
• Multiplication: Multiply the digital AM signal with the carrier.
• Filtering: Remove high-frequency components using a digital low-pass filter: an FIR was used in our project.
• Output: The resulting signal represents the recovered message.

Mathematics of AM Demodulation

The AM signal can be represented as:

Where:

• A_c = carrier amplitude
• f_c = carrier frequency
• m(t) = message signal

To demodulate digitally, multiply the AM signal with a locally generated carrier:

Using the identity cos²(x) = (1 + cos(2x))/2:

After low-pass filtering, high-frequency terms are removed:

The original message is recovered by scaling factor K: 

In discrete-time digital implementation:

s[n] = sampled AM signal
c[n] = digital carrier from DDS
y[n] = s[n] * c[n]
m[n] ≈ Scaler * LPF{y[n]}
        

Implementation in Vivado with VHDL

The AM demodulation process is implemented by multiplying the received AM signal with a locally generated carrier produced by a DDS. The resulting signal is then passed through a low-pass filter to extract the original message signal.

To demonstrate the outcome of this project, ee are using the AM modulated signal we generated in our previous project: It is a 1kHz message signal modulated with a 1600KHz carrier frequency. Below are the steps to follow to recover our message signal:

1. 1. Configure a new DDS to generate a carrier frequency of 1600KHz.
   2. Using a multiplier IP Core, Multiply the AM modulated signal with the generated carrier signal of 1600KHz.
   3. Create an low pass FIR filter to filter the signal obtained in step 2 above. Refer the FIR project I discussed previously to see how to create a new FIR for this project. The FIR I created for this project has the following requirements:
      • Sampling Frequency (f_s): 500 kHz
      • Passband Frequency (F_pass): 10 kHz
      • Stopband Frequency (F_stop): 20 kHz
      • Passband Ripple (A_pass): 1 dB
      • Stopband Attenuation (A_stop): 60 dB

Below is a copy of the VHDL code:

AM Demodulator – VHDL Top-Level Design

library ieee;
use ieee.std_logic_1164.all;
use IEEE.STD_LOGIC_SIGNED.ALL;
use ieee.numeric_std.all;

Library UNISIM;
use UNISIM.vcomponents.all;

entity AM_DeModulator_TopLevel is
  port (
    clk_p         : in  STD_LOGIC;
    clk_n         : in  STD_LOGIC;
    reset         : in  STD_LOGIC; 
    
    Dac_Out       : out std_logic_vector(11 downto 0); 
    ChipSeclect_n : out STD_LOGIC; 
    WriteEnable   : out STD_LOGIC
  );
end AM_DeModulator_TopLevel;

architecture behavioral of AM_DeModulator_TopLevel is

signal clk200MHz                : std_logic; 
signal clk400MHz                : std_logic;           
signal locked_Sig               : std_logic;
signal DDS0_tvalid_out          : std_logic;
signal CarrierFrequency         : std_logic_vector(15 downto 0); 

-- (code unchanged, preserved exactly as provided)

----------------------------------------------------------------
--This Process generates 500 KHz clock to be used by FIR
--signal valid input.
----------------------------------------------------------------
process(clk200MHz,reset)
    variable cnt : integer range 0 to 199 := 0;
begin
    if reset = '1' then
        cnt           := 0;
        FIR_Valid_in <= '0';

    elsif rising_edge(clk200MHz) then
        if cnt = 199 then
            cnt := 0;
            FIR_Valid_in <= not FIR_Valid_in;
        else
            cnt := cnt + 1;
        end if;
    end if;
end process;

end behavioral;